1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, a semiconductor device provided with a dummy electrode.
2. Description of the Background Art
In a flash memory NOR array of conventional art, a linear isolation insulating film and a linear active region are arranged parallel to each other on the surface of a substrate and extend in a first direction. Located on such a substrate, a linear gate electrode is disposed extending linearly in a second direction that is perpendicular to the first direction. There are a plurality of gate electrodes parallel to each other. When seen from above, a plurality of exposed regions of the surface of the substrate extending linearly and parallel to each other in gaps between the gate electrodes define source and drain regions, alternating with each other. In respective layers located above the gate electrodes, one of three types of metal interconnection is provided. The three types of interconnections are electrically connected to the gate electrode, the source region, and the drain region, respectively. Contact etching is generally known as a technique for connecting the source and drain regions with the corresponding metal interconnections.
As semiconductor devices are being continually downsized, the planar area of each section of the NOR array is required to be smaller. SAS (Self-Aligned Source) is known as a technique for facilitating the fabrication for a smaller width of the source region. SAS is disclosed in, for example, Japanese Patent Laying-Open No. 2002-26156.
In the SAS technique, the gate electrode is made before a resist is formed to cover the drain region and expose the source region. Then the resist and the gate electrode are used as a mask to etch away the portion of the isolation insulator that exist in the source region. Then, ion implantation is performed on each source region, thereby forming a diffused layer close to each source region of the surface of the substrate. Since the isolation insulator in the source region has already been removed, this diffused layer is continuous in the longitudinal direction of the source region. Thus, the diffused layer formed close to the source region of the surface of the substrate serves as a source interconnection that establishes electrical connection between the plurality of parallel active regions. Such a structure obtained by the SAS technique is called an “SAS structure”.
For an SAS structure, a high concentration of ion implantation to the source region is required in order to provide sufficiently low resistance in the source interconnection. Meanwhile, the width of the gate electrode is being reduced due to a smaller size of the device. With a smaller width of the gate electrode, an SAS structure having a conventional diffused layer of high concentration suffered a lack of the ability to sufficiently restrain the punch-through phenomenon encountered below the gate electrode.
Self-Aligned Contact (SAC) is generally known as the technique to stop contact etching by means of the insulating film protecting the gate electrode. The interlayer insulating film is formed of a material differing from that of the insulating film protecting the gate electrode, and the difference in selectivity is used during contact etching.
In order to avoid the punch-through phenomenon encountered in the SAS structure, SAC is sometimes employed in spite of a smaller width of the source region for etching to form a round contact hole connecting to the source region. In such cases, a stopper insulating film and sidewall insulating film made of SiN and the like initially covering the top surface and side of the gate electrode may be partially etched away during the etching step, whereby the gate electrode will be exposed directly in the contact hole. When a contact portion is formed by filling the contact hole with a conductive material, a short circuit will occur between the gate electrode and the contact portion. In other words, the gate is short-circuited to the source.